The present disclosure relates to aligning layers of an integrated circuit (IC) during manufacture, and more specifically, to an apparatus and method for using first and second diffraction gratings to align layers of an IC.
Advanced manufacturing of ICs requires formation of individual circuit elements, e.g., transistors such as field-effect-transistors (FETs) and the like, based on specific circuit designs. A FET generally includes source, drain, and gate regions. The gate region is placed between the source and drain regions and controls the current through a channel region (often shaped as a semiconductor fin) between the source and drain regions. Gates may be composed of various metals and often include a work function metal which is chosen to create desired characteristics of the FET. Transistors may be formed over a substrate and may be electrically isolated with an insulating dielectric layer, e.g., inter-level dielectric (ILD) layer. Contacts may be formed to each of the source, drain, and gate regions through the dielectric layer to connect the transistors to other circuit elements formed in other metal levels.
In the microelectronics industry as well as in other industries involving construction of microscopic structures (e.g., micromachines, magnetoresistive heads, etc.) there is a continued desire to reduce the size of structural features and microelectronic devices and/or to provide a greater amount of circuitry for a given chip size. Miniaturization in general allows for increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost. Present technology is at atomic level scaling of certain micro-devices such as logic gates, FETs, and capacitors. Circuit chips with hundreds of millions of such devices are common.
Photolithography is a technique for transferring an image rendered on one media onto another media photographically. Photolithography techniques are widely used in semiconductor fabrication. Typically, a circuit pattern is rendered as a positive or negative mask image which is then projected onto a silicon substrate coated with photosensitive materials (e.g., PR). Reticles are used to control radiation impingement on the masked surface to chemically change those areas of the coating exposed to the radiation, usually by polymerizing the exposed coating. The un-polymerized areas are removed, being more soluble in the developer than the polymerized regions, and the desired image pattern remains.
One challenge with advanced FinFET technology is ensuring proper alignment of parts during photolithography as the manufacturing process progresses. A photolithography reticle scanner identifies overlay marks on a layer of the wafer and precisely positions the reticle for the next layer relative to the wafer, e.g., to be used to pattern a mask used to form the layer. In some cases, parts of the circuit do not align as manufacturing progresses, creating an overlay shift, i.e., a misalignment. Grating asymmetry, i.e., dimensional differences or inconsistencies across different portions of a grating region, is considered a primary cause of misalignment in circuit manufacture. The intrinsic asymmetry of a grating pattern, i.e., reductions in contrast stemming from the design of a grating, may also contribute to misalignment between layers in some circumstances. Intrinsic grating asymmetry is especially problematic because known measurement techniques cannot account for intrinsic design features of an alignment mark.